MOS transistors or the MOSFET are well known. These transistors basically consist of a bar of doped silicon or some other substrate material that acts like a resistor. The terminal into which current is injected is called the source. The source terminal is similar in function to the cathode of a vacuum tube. The opposite terminal is called the drain terminal and can be likened to a vacuum tube plate. In a MOSFET, the polarity of the voltage applied to the drain and source can be changed. The gate electrode basically consists of a conductive area which is overlaid on the oxide covering the entire channel region. The conductive area of the gate in conjunction with the insulating oxide layer and the semiconductor channel forms a capacitor. Hence, by controlling the voltage on the gate electrode, one can control the current flowing between the source and the drain electrodes. Drain current flow is enhanced by the gate voltage and can be controlled or modulated by it. The channel resistance is directly related to the gate voltage. These operations are well known. It is possible to make a MOSFET with a P or N channel by reversing material conductivity types and it is also possible to form both P and N channel MOSFETs on the same substrate. This results in the complementary COS/MOS or CMOS types used in digital circuits.
As indicated, many variations of MOS devices exist. A difficulty which the prior art was well aware of concerning MOS devices relates to the protection of such devices. The prior art was aware of the fact that electrostatic discharges occur when an MOS device is picked up by its case and the handler's body capacitance to ground is discharged to ground through the series arrangements of the bulk-to-channel and channel-to-gate capacitances of the device. This applies to both discrete MOSFETs and complementary MOS ICs. Thus, the prior art taught one to handle such devices fairly carefully to prevent such damage. In any event, because of the static discharge problem, certain manufacturers provided some form of protection for a number of MOS devices. Generally, this protection takes the form of a diode incorporated as part of the substrate material.
By way of background illustration, the gate voltage handling capability of prior art MOS devices is between 30 volts and about 100 volts. Such voltages will not result in breakdown. However, with any MOS device, once the oxide insulation breaks down, the device is usually destroyed. Thus the prior art used a diode in parallel with the input capacitance and this method was employed in single gate MOS devices but had limitations in terms of signal handling as the single diode clips the positive peaks of a sine wave when the device is operated at near zero bias.
The use of a diode, as well as back-to-back diodes, was employed with MOS devices to prevent oxide breakdown for large voltages. The diodes were fabricated by forming a PN junction as part of the monolith chip. This protection scheme was used by many companies, such as Motorola, RCA, and so on in complementary MOS devices. Such protection circuits are well known. See, for example, a text entitled "Manual for MOS Users" by John D. Lenk, published by Reston Publishing Company, Inc. (1975). See also U.S. Pat. No. 4,061,928 entitled CIRCUIT ARRANGEMENT FOR THE PROTECTION OF INPUTS OF INTEGRATED MOS CIRCUITS, issued on Dec. 6, 1977 to H. H. Kessler and assigned to Siemens Aktiengesellschaft. This patent describes a circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages which may occur due to static charges. The circuit includes a first circuit connected to the MOS circuit and having two bypass circuits reacting at different input voltages, and having a high-ohmic compensating resistance. A second circuit is connected ahead of the first circuit and includes a bypass circuit and another high-ohmic compensating resistance. The circuit combination operates to protect the input to an inverter stage utilizing a MOSFET as an input transistor and another MOSFET as a load transistor.
U.S. Pat. No. 4,527,213, issued on Jul. 2, 1985, entitled SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH CIRCUITS FOR PROTECTING AN INPUT SECTION AGAINST AN EXTERNAL SURGE to S. Ariizumi. This patent shows a protection circuit for an MOS circuit which includes an input terminal having a first resistor connected at one end to the input terminal and a first protective circuit connected between the other end of the first resistor and a reference voltage source for accelerating the discharge of an input surge. The first protective circuit includes a first MOS transistor and a resistor connected in series to the source-drain path of the first transistor. The first transistor is wired as a diode having its gate electrode connected to the drain electrode, with a second circuit also connected as a diode having its gate electrode connected to the drain electrode, whereby the first and second circuits are separated by a resistor which is used to protect the MOS transistors with regard to large potentials.
See also U.S. Pat. No. 3,819,952 entitled SEMICONDUCTOR DEVICE, issued on Jun. 25, 1974 to T. Enomoto et al. This patent shows a first protected insulated gate field effect transistor having a drain and a source connected respectively to a gate and source of an FET to be protected against overvoltages, with the gate connected to an input through a resistor. A second protecting FET transistor, higher in threshold voltage than the first transistor, has a source connected to the gate of the first transistor and through another resistor to the source of the same transistor with its gate and drain coupled to the input. The second protecting transistor conducts in response to an overvoltage applied to the input to decrease the voltage applied to the protected transistor and to cause conduction of the first transistor. The conduction of the first transistor causes a voltage at a decreased level to be applied to the protected transistor. The circuit schematic is shown in FIGS. 2, 3, and 4 where field effect transistors are shown with the gate and sources connected together as a diode.
See also U.S. Pat. No. 4,481,521 entitled INSULATED GATE FIELD EFFECT TRANSISTOR PROVIDED WITH A PROTECTIVE DEVICE FOR A GATE INSULATING FILM, issued on Nov. 6, 1984 to K. Okumura. This patent shows an improved protective device for the gate insulation of an integrated gate field effect transistor (IGFET) that does not break down under spike-like input voltages. The protective device is formed on the same semiconductor chip as an operative IGFET and includes a resistor connected between the input terminal and the operative IGFET's gate. The protection IGFET has the drain and gate both connected to the operative IGFET's gate, and another resistor connected between the protection IGFET's source and a constant voltage source completes the circuit.
The above patents and prior art have been cited to acknowledge the fact that there are many prior art disclosures which relate to protection devices and circuits for protecting the gate insulating film to extend the life of the protected field effect device. The prior art is aware that an improved electrical performance of an FET can be had by decreasing the threshold voltage and increasing the voltage gain by making the gate insulating film thinner. However, if the gate insulating film is made thinner, the dielectric breakdown voltage of the gate insulating film is lowered. Thus, it is desirable to keep the gate insulating film as thin as possible but to also provide protection so that the thin gate insulating film is not destroyed during a device over voltage.
There is a particular problem which involves a series pass-through MOSFET which is employed in many MOS circuit configurations. In many system configurations which utilize series pass-through MOSFETs, the circuits employ two different voltages which are supplied from different power supplies. For example, in such a system one may use a 3.3 volt and a 5 volt supply for biasing and providing logic levels. The 3.3 volt power source may not necessarily be on when the 5 volt supply is turned on. This can occur during "Power On" for a short period of time or due to a malfunction of one supply as the lower voltage supply for any given period of time. In this case, the input/output circuits of the 3.3 volt circuit components are biased with 5.5 volts which can cause, in the case of thin gate oxides (those having thicknesses of 10 nm or below), a severe oxide stress with related damage. Prior art techniques do not address themselves to the protection of a MOSFET used as a series pass-through device. Furthermore, one requires a thin oxide and if the oxide were made thicker to avoid the problem, then the device would exhibit lower transconductance leading to decreased circuit performance.
As will be further explained, the present invention allows the use of a thin oxide device with high transconductance in the input/output circuitry in conjunction with a series pass or a pass-through MOSFET.